PHY Receiver Interface¶

The PHY Receiver IP core must be instantiated in the FPGA design along with other required cores. The PHY Rx core also requires a CPU in the FPGA design for configuration and control from software.

The PHY Receiver core port are described below.

Clocks and Resets¶

The Rx PHY core has a single clock domain that must be synchronous to the IQ sample stream. Any clock domain crossing logic must be implemented outside the Rx PHY core. In Mango reference designs with ADI radios the clock domain cross is implemented in the wlan_phy_rx_iq_cdc utility core.

Port	Direction	Data Type	Description
`clk`	Input	`UFix1_0`	Clock input, must be synchronous to and at least 4x faster than the IQ sampling rate. Typically this is connected to a 160MHz clock that is synchronzied to the radio reference clock.
`phy_rx_reset`	Input	`UFix1_0`	Synchronous active-high reset to all state in Rx processing pipeline. This reset does not clear registers in the AXI slave interface.
`wlan_phy_rx_aresetn`	Input	`UFix1_0`	Asynchronous active-low reset for AXI interface logic. This reset does not clear registers in the AXI slave interface. This signal should be connected to the same reset as the AXI infrastructure cores.

AXI Slave Interface¶

The Rx PHY IP core implements an AXI4-Lite slave interface with many configuration and status registers. The FPGA design must connect this AXI slave interface to an AXI master, typically an AXI interconnect and CPU. The CPU must configure the Rx PHY IP core at boot by writing the core’s registers.

The Rx core’s AXI interface appears as a bus named wlan_phy_rx_regs_s_axi in the Vivado tools. This bus interface wraps all the inputs/outputs which implement the AXI interface.

Packet Buffer Block RAM Interface¶

The Rx PHY IP core implements a block RAM master interface. The FPGA design must connect this interface to one port of a dual-port 32KB block RAM. The other block RAM port must be accessible by the CPUs in the FPGA design.

This block RAM implements the 8 packet buffers required by the MAC software. The Rx PHY core writes packet data directly to the packet buffer block RAM during a reception.

Port	Direction	Data Type	Description
`bram_addr`	Output	`UFix31_0`	Address, connect to block RAM `addr` port
`bram_din`	Input	`UFix63_0`	Data in, connect to block RAM `dout` port; the Rx PHY ignores this input
`bram_wen`	Output	`UFix7_0`	Write enable, connect to block RAM `we` port
`bram_dout`	Output	`UFix63_0`	Data output, connect to block RAM `din` port
`bram_en`	Output	`UFix1_0`	RAM enable, connect to block RAM `en` port
`bram_reset`	Output	`UFix1_0`	RAM reset, connect to block RAM `rst` port

MAC Support Core Interface¶

The following ports must be connected to the MAC Support Core (wlan_mac_hw) in the FPGA design.

Port	Direction	Data Type	Description
`phy_rx_block_pktdet`	Input	`UFix1_0`	When asserted blocks any new receptions, does not interrupt ongoing reception. Asserted by MAC hardware to ensure a reception is not overwritten before it is processed by software.
`phy_cca_ind_busy`	Output	`UFix1_0`	Indicates Rx PHY observes a busy medium, connected to MAC hardware’s CCA logic.
`phy_rx_data_byte`	Output	`UFix8_0`	Latest byte decoded by Rx PHY, valid when `phy_rx_data_ind` is high
`phy_rx_data_bytenum`	Output	`UFix1_0`	Index of latest byte decoded by Rx PHY, valid when `phy_rx_data_ind` is high
`phy_rx_data_ind`	Output	`UFix1_0`	Asserts when `data_byte` and `data_bytenum` outputs are valid
`phy_rx_data_done_ind`	Output	`UFix1_0`	Asserts when last byte of a packet has been decoded and written to the packet buffer
`phy_rx_end_ind`	Output	`UFix1_0`	Asserts at MAC’s `RX_END` envent (extension period after last sample on medium)
`phy_rx_end_rxerror`	Output	`UFix2_0`	Asserts when an Rx event ends with an error, typically a decoding error in the PHY header
`phy_rx_fcs_good_ind`	Output	`UFix1_0`	Asserts if packet checksum was valid, valid when `phy_rx_data_done_ind` is asserted
`phy_rx_phy_hdr_ind`	Output	`UFix1_0`	Asserts when a PHY header has been decoded and can safely be processed by MAC software
`phy_rx_phy_hdr_length`	Output	`UFix16_0`	LENGTH field decoded from PHY header, valid when `phy_rx_phy_hdr_ind` is asserted
`phy_rx_phy_hdr_mcs`	Output	`UFix7_0`	MCS field decoded from PHY header, valid when `phy_rx_phy_hdr_ind` is asserted
`phy_rx_phy_hdr_phy_mode`	Output	`UFix2_0`	Waveform type (0=DSSS, 1=NONHT, 2=HTMF) of received packet, valid when `phy_rx_phy_hdr_ind` is asserted
`phy_rx_phy_hdr_unsupported`	Output	`UFix1_0`	Asserts when PHY header indicates packet requires features not supported by PHY, valid when `phy_rx_phy_hdr_ind` is asserted
`phy_rx_start_ind`	Output	`UFix1_0`	Asserts when Rx PHY has started receiving a new packet
`phy_rx_start_phy_sel`	Output	`UFix1_0`	Indicates whether new reception is DSSS (0) or OFDM (1), valid when `phy_rx_start_ind` is asserted

Radio Interface¶

The following ports must be connected to the radio interface in the FPGA design.

Port	Direction	Data Type	Description
`rf_X_iq_valid`	Inputs	`UFix1_0`	Indicates signals on `rf_X_<i,q>` are valid, maximum rate is 1/4 of the `clk` input
`rf_a_<i,q>`	Inputs	`Fix16_11`	Complex baseband (IQ) samples from RF A interface
`rf_b_<i,q>`	Inputs	`Fix16_11`	Complex baseband (IQ) samples from RF B interface

Debug Signals¶

The Rx PHY connects many internal signals to top-level ports identified by the dbg_ prefix. These ports can be routed to top-level FPGA pins or on-chip ILA cores for easier debugging in hardware. The selection of ports varies with Rx PHY core version.