PHY Receiver Register Map¶

The PHY Receiver IP core implements an AXI4-Lite slave interface which must be be connected to a CPU in the FPGA design. The software must configure and control the Rx PHY by accessing registers via this AXI interface.

The name and contents of each register are detailed below. The register address offsets are chosen automatically by System Generator when the IP core is exported. The actual address offsets are defined in the wlan_phy_rx_pmd_hw.h header file written by System Generator during the export process.

All software-accessible registers are 32 bits wide. Each register is either read/write (“Gateway In” block in the Sysgen model) or read-only (“Gateway Out” block).

Individual register fields have specific System Generator data types. Datatype descriptions below use the standard System Generator syntax, where UFixM_N and FixM_N refer to unsigned and signed fixed-point values with M total bits and binary point N.

Register List¶

Name	Access	Description
`CONTROL`	RW	Low-level resets
`RX_CONFIG`	RW	General configuration register
`RAMS_ADDR_WREN`	RW	DSSS SYNC Matching Addr - WrEn
`MASK_1_RAM_WR_DATA`	RW	DSSS Sync Matching Mask Wr Data
`TARGET_RAM_WR_DATA`	RW	DSSS Sync Matching Bits Wr Data
`PKT_BUF_SEL`	RW	Packet buffer interface config
`PKTDET_DSSS_CONFIG`	RW	DSSS packet detection config
`PKTDET_AUTOCORR_CONFIG`	RW	Auto-correlation packet detector configuration
`PKTBUF_MAX_WRITE_ADDR`	RW	Max allowed pkt buf write address configuration
`PHY_CCA_CONFIG`	RW	Physical carrier sensing (CCA) configuration
`RXIQ_SCALE`	RW	Scaling values for Rx IQ
`LTS_CORR_THRESH`	RW	LTS correlation thresholds
`LTS_CORR_PEAKTYPE_THRESH`	RW	LTS correlation peak type threshold
`LTS_CORR_CONFIG`	RW	LTS correlator configuration
`IQMAG_PHYS_CS_CONFIG`	RW	IQ-magnitude-based physical carrier sense configuration
`FFT_CONFIG`	RW	FFT core configuration
`FEC_CONFIG`	RW	FEC decoder configuration
`DSSS_RX_CONFIG`	RW	DSSS Rx PHY configuration
`CHAN_EST_SMOOTHING`	RW	OFDM channel estimate smoothing configuration
`CFO_EST_TIME_DOMAIN`	RO	CFO estimate from time-domain LTF
`LTF_DET_COUNT`	RO	LTF Det Event Count
`PKT_DET_COUNT_DSSS`	RO	DSSS Pkt Det Event Count
`PKT_DET_COUNT_OFDM`	RO	OFDM Pkt Det Event Count
`RX_GAIN_INDEX_CAPT`	RO	Current packet Rx gain index
`RX_IQ_MAG_CAPT_RFAB`	RO	Current packet IQ magnitude
`STATUS`	RO	Status register

Register `CONTROL`¶

Name	Bits	Datatype	Description
`RESET_STATS_COUNTERS`	1	`UFix1_0`	Resets the stats counters
`RESET`	0	`UFix1_0`	Resets all state in DSSS and OFDM pipelines, does not clear registers

Register `RX_CONFIG`¶

Name	Bits	Datatype	Description
`OFDM_REQ_PKT_DET`	30	`UFix1_0`	Disables LTF-det-only OFDM receptions, requires packet detection before OFDM Rx
`SYNC_MATCH_PKT_DET_BLOCK`	29	`UFix1_0`	Blocks pkt det events after a DSSS SYNC match
`RFB_IQMAG_PHYS_CS_EN`	28	`UFix1_0`	Enables physical carrier sense based on Rx IQ magnitude on RF B
`RFA_IQMAG_PHYS_CS_EN`	27	`UFix1_0`	Enables physical carrier sense based on Rx IQ magnitude on RF A
`VHT_DET_EN`	25	`UFix1_0`	Enables detection of VHT waveforms based on BPSK rotation in VHTSIG symbols
`HT_DET_EN`	24	`UFix1_0`	Enables detection of HT waveforms based on BPSK rotation in HTSIG symbols
`DSSS_RX_CCA_EN`	23	`UFix1_0`	Sets CCA output to BUSY when DSSS pipeline is receiving a packet
`CCA_RATE_LEN_EN`	22	`UFix1_0`	Sets CCA output to BUSY for duration of packet based on SIGNAL field rate/length; must be enabled for normal DCF operation
`MAX_SIGNAL_LEN`	20:17	`UFix4_0`	Sets maximum allowed value for SIGNAL LENGTH field, in units of kB; set to 2 for normal DCF operation
`ANT_SEL`	16:15	`UFix2_0`	Selects current RF interface for all receptions, 0=RF A, 1=RF B
`EXT_PKT_DET_EN`	13	`UFix1_0`	Enables the PKT_DET_IN input port as alternate source of packet detection events; set to 0 for normal operation
`RFB_PKT_DET_EN`	10	`UFix1_0`	Enables packet detections on RF B
`RFA_PKT_DET_EN`	9	`UFix1_0`	Enables packet detections on RF A
`OFDM_RX_DIS`	8	`UFix1_0`	Disables all OFDM receptions; set to 0 for normal operation
`CHAN_EST_LOG_EN`	6	`UFix1_0`	Enables writing of OFDM channel estimates to Rx packet buffer; set to 1 for normal operation
`BYPASS_CFO_EST`	5	`UFix1_0`	Disables time-domain CFO estimation and correction; set to 0 for normal operation
`BYPASS_CFO_EST`	5	`UFix1_0`	Disables time-domain CFO estimation and correction; set to 0 for normal operation
`DSSS_REQ_PKT_DET`	4	`UFix1_0`	Sets DSSS Rx to require auto-correlation pkt det before attempting reception
`CHAN_EST_ENDIAN`	3	`UFix1_0`	Sets the byte order for channel estimates written to packet buffer; set to 0 for normal (little-endian) operation
`PKT_BUF_ENDIAN`	2	`UFix1_0`	Sets the byte order for writing bytes to Rx packet buffer; set to 1 for normal (little-endian) operation
`DSSS_RX_EN`	0	`UFix1_0`	Enables DSSS receptions; set to 1 for normal operation

Register `RAMS_ADDR_WREN`¶

Name	Bits	Datatype	Description
`MASK_WREN`	25	`UFix1_0`	Write-enable for SYNC Matching Mask RAM
`TARGET_WREN`	24	`UFix1_0`	Write-enable for SYNC Matching Data RAM
`WR_ADDR`	15:0	`UFix16_0`	Write address for SYNC Matching RAMs

Register `MASK_1_RAM_WR_DATA`¶

Name	Bits	Datatype	Description
`SYNC_MATCH_DATA`	31:0	`UFix32_0`	32-bit word written to DSSS SYNC matching mask RAM

Register `TARGET_RAM_WR_DATA`¶

Name	Bits	Datatype	Description
`SYNC_MATCH_DATA`	31:0	`UFix32_0`	32-bit word written to DSSS SYNC matching target RAM

Register `PKT_BUF_SEL`¶

Name	Bits	Datatype	Description
`CHAN_EST_OFFSET`	31:24	`UFix8_0`	Byte offset into packet buffer for writing OFDM channel estimates
`RX_OFFSET`	23:16	`UFix8_0`	Byte offset into packet buffer for writing received bytes
`DSSS_PKT_BUF_SEL`	11:8	`UFix4_0`	Rx packet buffer index for DSSS receptions
`OFDM_PKT_BUF_SEL`	3:0	`UFix4_0`	Rx packet buffer index for OFDM receptions

Register `PKTDET_DSSS_CONFIG`¶

Name	Bits	Datatype	Description
`DET_MAG_THRESH`	21:8	`UFix14_3`	Minimum magnitude of Rx samples for packet detection
`DET_CORR_THRESH`	7:0	`UFix8_8`	Normalized auto-correlation threshold for packet detection

Register `PKTDET_AUTOCORR_CONFIG`¶

Name	Bits	Datatype	Description
`RESET_EXT_DUR`	31:26	`UFix6_0`	Duration of post-pkt-det reset during which no detections will occur, in units of 16x `proc_clk` cycles
`DET_MIN_DUR`	25:22	`UFix4_0`	Minimum duration of correlation above threshold to assert packet detection, in units of Rx samples
`DET_MAG_THRESH`	21:8	`UFix14_3`	Minimum magnitude of Rx samples for packet detection
`DET_CORR_THRESH`	7:0	`UFix8_8`	Normalized auto-correlation threshold for packet detection

Register `PKTBUF_MAX_WRITE_ADDR`¶

Name	Bits	Datatype	Description
`PKTBUF_MAX_WRITEADDR`	31:0	`UFix32_0`	Largest byte address Rx PHY is allowed to write in each Rx packet buffer

Register `PHY_CCA_CONFIG`¶

Name	Bits	Datatype	Description
`CCA_POST_RX_EXT`	23:16	`UFix8_0`	Duration of extension from last sample received to de-assertion of CCA busy, in units of Rx sample period

Register `RXIQ_SCALE`¶

Name	Bits	Datatype	Description
`I_Scaling`	31:16	`UFix16_0`	Scaling value for Rx I input
`Q_Scaling`	15:0	`UFix16_0`	Scaling value for Rx Q input

Register `LTS_CORR_THRESH`¶

Name	Bits	Datatype	Description
`LTS_CORR_THRESH`	15:0	`UFix16_0`	Threshold for LTS cross correlation

Register `LTS_CORR_PEAKTYPE_THRESH`¶

Name	Bits	Datatype	Description
`LTS_CORR_PEAKTYPE_THRESH`	15:0	`UFix16_0`	Threshold for classifying correlation peaks as Big or Small

Register `LTS_CORR_CONFIG`¶

Name	Bits	Datatype	Description
`LTS_CORR_PEAK_DLY_MASKS`	26:24	`UFix3_0`	Configures allowed delays between LTS correlation peaks; one-hot encoded, 1=63, 2=64, 4=65
`LTS_TIMEOUT`	7:0	`UFix8_0`	Timeout period for missing LTS correlation after packet detection event, in units of 2 sample periods

Register `IQMAG_PHYS_CS_CONFIG`¶

Name	Bits	Datatype	Description
`IQ_PHYSCS_THRESH`	15:0	`UFix16_8`	Physical carrier sense threshold based on IQ magnitude

Register `FFT_CONFIG`¶

Name	Bits	Datatype	Description
`FFT_SCALING`	29:24	`UFix6_0`	Scaling configuration for FFT core, should be set to `0x05`; refer to Xilinx FFT core datasheet for details on scaling modes
`FFT_OFFSET`	23:16	`UFix8_0`	Configures FFT window shift in each OFDM symbol; `2` selects zero cyclic prefix samples; set to `4` for normal operation
`CP_LEN`	15:8	`UFix8_0`	Number of cyclic prefix samples, must be set to `16`
`NUM_SC`	7:0	`UFix8_0`	Number of subcarriers, must be set to `64`

Register `FEC_CONFIG`¶

Name	Bits	Datatype	Description
`FEC_SCALE_64QAM`	19:15	`UFix5_0`	Scaling for 64-QAM soft bits
`FEC_SCALE_16QAM`	14:10	`UFix5_0`	Scaling for 16-QAM soft bits
`FEC_SCALE_QPSK`	9:5	`UFix5_0`	Scaling for QPSK soft bits
`FEC_SCALE_BPSK`	4:0	`UFix5_0`	Scaling for BPSK soft bits

Register `DSSS_RX_CONFIG`¶

Name	Bits	Datatype	Description
`SYNC_SEARCH_TIME`	31:24	`UFix8_0`	Duartion after first SYNC match to select best branch index, in units of Rx sample periods
`SFD_SEARCH_TIMEOUT`	23:16	`UFix8_0`	Timeout duration after packet detection for SFD search, in units of Rx sample periods
`SYNC_SEARCH_TIMEOUT`	15:8	`UFix8_0`	Timeout duration after packet detection for SYNC search, in units of Rx sample periods
`SYNC_SEARCH_THRESH`	7:0	`UFix8_0`	Matching threshold for SYNC search

Register `CHAN_EST_SMOOTHING`¶

Name	Bits	Datatype	Description
`PHY_MODE_DET_THRESH`	29:24	`UFix6_0`	Threshold compared to abs(I-Q) when determining BPSK/QAM in HT-SIG symbols
`CHAN_EST_SMOOTH_COEF_B`	23:12	`UFix12_12`	Channel estimate smoothing coefficient B; set to zero
`CHAN_EST_SMOOTH_COEF_A`	11:0	`UFix12_12`	Channel estimate smoothing coefficient B; set to 0xFFF

Register `CFO_EST_TIME_DOMAIN`¶

Name	Bits	Datatype	Description
`CFO_EST`	31:0	`Fix32_31`	CFO estimate for current packet captured after preamble

Register `LTF_DET_COUNT`¶

Name	Bits	Datatype	Description
`LTF_DET_COUNT`	31:0	`UFix32_0`	Number of packets detected with only LTF detection

Register `PKT_DET_COUNT_DSSS`¶

Name	Bits	Datatype	Description
`PKT_DET_COUNT_DSSS`	31:0	`UFix32_0`	Number of DSSS packet detection events

Register `PKT_DET_COUNT_OFDM`¶

Name	Bits	Datatype	Description
`PKT_DET_COUNT_OFDM`	31:0	`UFix32_0`	Number of OFDM packet detection events

Register `RX_GAIN_INDEX_CAPT`¶

Name	Bits	Datatype	Description
`RX_GAIN_INDEX_CAPT`	31:0	`UFix32_0`	Rx gain index for current reception, captured after preamble

Register `RX_IQ_MAG_CAPT_RFAB`¶

Name	Bits	Datatype	Description
`RX_IQ_MAG_CAPT_RFA`	31:16	`Fix16_8`	Current packet summed IQ magnitude on RF A captured after preamble
`RX_IQ_MAG_CAPT_RFA`	15:0	`Fix16_8`	Current packet summed IQ magnitude on RF A captured after preamble

Register `STATUS`¶

Name	Bits	Datatype	Description
`PKT_DET_STATUS_DSSS`	10:9	`UFix2_0`	Indicates which RF interfaces have DSSS packet detection asserted; 1=RF A, 2=RF B
`PKT_DET_STATUS_OFDM`	8:4	`UFix5_0`	Indicates which RF interfaces have OFDM packet detection asserted; 1=RF A, 2=RF B, 16=Ext pkt det
`ANT_SEL`	3:2	`UFix2_0`	Indicates antenna selection for last reception; 1=RF A, 2=RF B
`DSSS_FCS_GOOD`	1	`UFix1_0`	Indictes last DSSS reception had good checksum
`OFDM_FCS_GOOD`	0	`UFix1_0`	Indictes last OFDM reception had good checksum

PHY Receiver Register Map¶

Register List¶

Register CONTROL¶

Register RX_CONFIG¶

Register RAMS_ADDR_WREN¶

Register MASK_1_RAM_WR_DATA¶

Register TARGET_RAM_WR_DATA¶

Register PKT_BUF_SEL¶

Register PKTDET_DSSS_CONFIG¶

Register PKTDET_AUTOCORR_CONFIG¶

Register PKTBUF_MAX_WRITE_ADDR¶

Register PHY_CCA_CONFIG¶

Register RXIQ_SCALE¶

Register LTS_CORR_THRESH¶

Register LTS_CORR_PEAKTYPE_THRESH¶

Register LTS_CORR_CONFIG¶

Register IQMAG_PHYS_CS_CONFIG¶

Register FFT_CONFIG¶

Register FEC_CONFIG¶

Register DSSS_RX_CONFIG¶

Register CHAN_EST_SMOOTHING¶

Register CFO_EST_TIME_DOMAIN¶

Register LTF_DET_COUNT¶

Register PKT_DET_COUNT_DSSS¶

Register PKT_DET_COUNT_OFDM¶

Register RX_GAIN_INDEX_CAPT¶

Register RX_IQ_MAG_CAPT_RFAB¶

Register STATUS¶