PHY Transmitter Interface¶
The PHY Transmitter IP core must be instantiated in the FPGA design along with other required cores. The PHY Tx core also requires a CPU in the FPGA design for configuration and control from software.
The PHY Transmitter core port are described below.
Clocks and Resets¶
The Tx PHY core implements two clock domains - Sampling Clock and Processing Clock domains.
The Sampling Clock domain implements the I/Q outputs to the radio interface DACs. These outputs are driven by a clock-domain-crossing FIFO. The Sampling Clock must be synchronous to the radio interface logic.
The Processing Clock domain implements the complete 802.11 Tx pipeline. The Processing Clock is typically synchronous to the CPU and AXI infrastructure clocks.
| Port | Direction | Data Type | Description |
|---|---|---|---|
tx_phy_pipeline_proc_clk_clk |
Input | UFix1_0 |
Processing clock input, must be at least 4x faster than the sampling rate (toggling rate of rf_tx_iq_rd_en input) |
tx_phy_interface_samp_clk_clk |
Input | UFix1_0 |
Sampling clock input |
tx_reset |
Input | UFix1_0 |
Synchronous active-high reset to all state in Tx processing pipeline. This reset does not clear registers in the AXI slave interface. |
tx_phy_pipeline_proc_clk_aresetn |
Input | UFix1_0 |
Asynchronous active-low reset for AXI interface logic. This reset does not clear registers in the AXI slave interface. This signal should be connected to the same reset as the AXI infrastructure cores. |
AXI Slave Interface¶
The Tx PHY IP core implements an AXI4-Lite slave interface with many configuration and status registers. The FPGA design must connect this AXI slave interface to an AXI master, typically a CPU. The CPU must configure the Tx PHY IP core at boot by writing the core’s registers.
The Tx core’s AXI interface appears as a bus named tx_phy_pipeline_proc_clk_regs_s_axi in the Vivado tools. This bus interface wraps all the inputs/outputs which implement the AXI interface.
Packet Buffer Block RAM Interface¶
The Tx PHY IP core implements a block RAM master interface. The FPGA design must connect this interface to one port of a dual-port 64KB block RAM. The other block RAM port must be accessible by the CPUs in the FPGA design. The block RAM must be in the Processing Clock domain.
This block RAM implements the 16 packet buffers required by the MAC software. The Tx PHY core reads packet data directly from the packet buffer block RAM during a transmission.
| Port | Direction | Data Type | Description |
|---|---|---|---|
bram_addr |
Output | UFix31_0 |
Address, connect to block RAM addr port |
bram_din |
Input | UFix63_0 |
Data in, connect to block RAM dout port |
bram_wen |
Output | UFix7_0 |
Write enable, connect to block RAM we port. The Tx PHY ties this port to zero. |
bram_dout |
Output | UFix63_0 |
Data output, connect to block RAM din port. The Tx PHY ties this port to zero. |
bram_en |
Output | UFix1_0 |
RAM enable, connect to block RAM en port |
bram_reset |
Output | UFix1_0 |
RAM reset, connect to block RAM rst port |
MAC Support Core Interface¶
The following ports must be connected to the MAC Support Core (wlan_mac_hw) in the FPGA design. These signals are in the Processing Clock domain.
| Port | Direction | Data Type | Description |
|---|---|---|---|
phy_tx_start |
Input | UFix1_0 |
Rising edge starts new transmission |
phy_tx_pkt_buf |
Input | UFix4_0 |
Index of packet buffer containing packet to transmit; captured on rising edge of phy_tx_start |
phy_tx_phy_mode |
Input | UFix2_0 |
Selects waveform format for transmission (1=NONHT, 2=HTMF); captured on rising edge of phy_tx_start |
phy_tx_ant_mask |
Input | UFix4_0 |
One-hot value selects which antenna outputs are active for transmission; captured on rising edge of phy_tx_start |
phy_tx_phy_mode |
Input | UFix2_0 |
Selects waveform format for transmission (1=NONHT, 2=HTMF); captured on rising edge of phy_tx_start |
phy_tx_gain_X |
Input | UFix6_0 |
Tx gain indexes passed through to rc_tx_gain_X output at start of transmission; captured on rising edge of phy_tx_start |
phy_tx_started |
Output | UFix1_0 |
Asserts when first sample is output from Tx PHY to DACs |
phy_tx_done |
Output | UFix1_0 |
Pulses high after last sample is output from Tx PHY to DACs |
I/Q Sample Interface¶
The following ports must be connected to the radio interface in the FPGA design. These signals are in the samp_clk clock domain.
| Port | Direction | Data Type | Description |
|---|---|---|---|
rf_tx_iq_rd_en |
Input | UFix1_0 |
High level on this input outputs new IQ sample on all IQ outputs. The radio interface must drive this signal at the rate at which it requires samples. |
rf_a_tx_<i,q> |
Outputs | Fix16_15 |
Complex baseband (IQ) samples for RF A interface |
rf_b_tx_<i,q> |
Outputs | Fix16_15 |
Complex baseband (IQ) samples for RF B interface |