PHY Transmitter Register Map¶

The PHY Transmitter IP core implements an AXI4-Lite slave interface which must be be connected to a CPU in the FPGA design. The software must configure and control the Tx PHY by accessing registers via this AXI interface.

The name and contents of each register are detailed below. The register address offsets are chosen automatically by System Generator when the IP core is exported. The actual address offsets are defined in the wlan_phy_tx_pmd_hw.h header file written by System Generator during the export process.

All software-accessible registers are 32 bits wide. Each register is either read/write (“Gateway In” block in the Sysgen model) or read-only (“Gateway Out” block).

Individual register fields have specific System Generator data types. Datatype descriptions below use the standard System Generator syntax, where UFixM_N and FixM_N refer to unsigned and signed fixed-point values with M total bits and binary point N.

Register List¶

Name	Access	Description
`TX_START`	RW	Tx start control bits (only for software-initiated Tx events)
`TX_CONFIG`	RW	Configuration bits
`TIMING`	RW	Post-Tx Timing values
`PKT_BUF_SEL`	RW	Packet buffer selection and interface config
`PHY_START_DELAY`	RW	Tx start delay configuration
`OUTPUT_SCALING`	RW	Post-Tx Timing values
`FFT_CONFIG`	RW	FFT core configuration
`STATUS`	RO	Tx core status

Register `TX_START`¶

Name	Bits	Datatype	Description
`TX_START_DIRECT`	0	`UFix1_0`	Immediately starts a new software-initiated transmission from the packet buffer selected by the `Pkt_Buf_Sel` value. This field should only be used for testing the Tx PHY alone; in the full FPGA design the Tx PHY is started by the MAC support core via the `TX_START.IND` port.

Register `TX_CONFIG`¶

Name	Bits	Datatype	Description
`RESET`	31	`UFix1_0`	Resets all state in the Tx pipeline, does not reset registers
`PHY_MODE`	14:12	`UFix3_0`	Sets the PHY mode (1=NONHT, 2=HTMF) for software-initiated transmissions; PHY mode is typically set by the MAC support core via the `PHY_TX_PHY_MODE` input port
`RESET_SIGNAL_ERRS`	9	`UFix1_0`	Resets the latches which capture `SIGNAL` field decoding errors
`TX_START_SEL`	8	`UFix1_0`	Selects which event starts the Tx PHY pipeline; `0` selects the `RC_PHY_START` input port, `1` selects a programmed delay after the `PHY_TX_START` input port
`USE_MAC_ANTMASKS`	6	`UFix1_0`	Enables the `PHY_TX_ANT_MASK` input port, giving control of Tx antenna selection to the MAC support core
`ANTB_TX_EN`	3	`UFix1_0`	Enables the I/Q outputs to the RF B interface; can be overridden by the antenna selection value provided by the MAC core in hardware
`ANTA_TX_EN`	2	`UFix1_0`	Enables the I/Q outputs to the RF A interface; can be overridden by the antenna selection value provided by the MAC core in hardware
`RESET_SCRBL_PERTX`	1	`UFix1_0`	When asserted the Tx PHY resets the scrambler on every transmission; set to 0 for pseudo-random initial scrambler state per transmission.
`RC_RXEN_ENABLE`	0	`UFix1_0`	Asserts the RC_RXEN output when the Tx PHY is not transmitting

Register `TIMING`¶

Name	Bits	Datatype	Description
`POST_TX_RX_SIGS_INVALID`	29:20	`UFix10_0`	Delay between the last sample output to the DACs and de-assertion of the `RX_SIGS_INVALID` output, in units of 4 `proc_clk` cycles
`POST_TXEN_EXTENSION`	19:10	`UFix10_0`	Delay between the last sample output to the DACs and de-assertion of the `RX_USR_TXEN` outputs, in units of 4 `proc_clk` cycles
`POST_TX_EXTENSION`	9:0	`UFix10_0`	Delay between the last sample output to the DACs and assertion of the `TX_END.IND` output to the MAC, in units of 4 `proc_clk` cycles

Register `PKT_BUF_SEL`¶

Name	Bits	Datatype	Description
`PKT_BUYF_ADDR_OFFSET`	23:16	`UFix8_0`	Sets the byte index of the start of the PHY header in Tx packet buffers, typically set to `sizeof(tx_frame_info_t)` by MAC software. Must be a multiple of 8.
`PKT_BUF_SEL`	3:0	`UFix4_0`	Selects the Tx packet index, only used for software-initiated transmissions. Packet buffer is typically selected by the MAC support core via the `PHY_TX_PKT_BUF` input port.

Register `PHY_START_DELAY`¶

Name	Bits	Datatype	Description
`PHY_START_DELAY`	13:0	`UFix14_0`	Sets delay between assertion of `TX_START.IND` by MAC core and start of Tx pipeline, in units of 4 `proc_clk` cycles

Register `OUTPUT_SCALING`¶

Name	Bits	Datatype	Description
`TX_SCALING`	15:0	`UFix16_12`	Sets digital scaling at output of Tx pipeine before samples are fed to DACs

Register `FFT_CONFIG`¶

Name	Bits	Datatype	Description
`FFT_SCALING`	29:24	`UFix6_0`	Scaling configuration for FFT core, should be set to `0x2A`; refer to Xilinx FFT core datasheet for details on scaling modes
`CP_LEN`	15:8	`UFix8_0`	Number of cyclic prefix samples, must be set to `16`
`NUM_SC`	7:0	`UFix8_0`	Number of subcarriers, must be set to `64`

Register `STATUS`¶

Name	Bits	Datatype	Description
`SIG_DECODE_ERRS`	3:1	`UFix3_0`	Error code when Tx PHY cannot decode `SIGNAL` field as provided by MAC sofware in Tx packet buffer
`TX_RUNNING`	0	`UFix1_0`	Indicates Tx PHY is active; asserts when software or hardware initiates a transmission, de-asserts after Tx extension after last sample output to DACs