2.1. Vivado Project

The 802.11 FPGA Design is implemented as a Xilinx Vivado IP Integrator (IPI) block diagram. The IPI block diagram instantiates each IP core in the FPGA Design and defines the connectivity between every core and to off-chip peripherals. The IPI block diagram implements the complete FPGA design. The block diagram becomes the hardware project exported to the SDK for use with the 802.11 MAC software via the Vivado synthesis and implementation flows.

Mango provides pre-built Vivado projects for reference hardware platforms. This section describes how to re-create the Vivado project. This is only required for users who wish to modify the reference FPGA design.

Prerequisites

Please review the following requirements before using the 802.11 FPGA Design.

Vivado Tools

Each release of the 802.11 FPGA Design is built in a specific version of the Xilinx Vivado tools.

The current 802.11 FPGA Design requires Xilinx Vivado 2022.2 or Xilinx Vivado 2024.2.

Using the 802.11 FPGA Design requires familiarity with the Xilinx Vivado design tools. The 802.11 design is built in the Vivado IDE and Xilinx SDK. The 802.11 FPGA design is implemented as an IP Integrator (IPI) block diagram. The IPI design integrates the PHY cores, peripheral controllers, AXI interconnects, CPUs, and all board-level constraints. The 802.11 MAC software design is implemented in the Xilinx SDK.

Users must be comfortable with the Vivado tools before being productive with the 802.11 FPGA Design. Xilinx provides extensive Vivado documentation and Vivado training

Project Path

The Vivado tools have specific requirements for project paths (folder and file names). There are additional path restrictions on Windows.

  • Paths must contain only letters, numbers and simple (ASCII) punctuation.
  • Paths must not contain spaces.
  • Use short folder names on Windows (max path length is 255 characters; Vivado creates many intermediate files with long names)

On Windows we recommend creating a root folder for the 802.11 FPGA Design such as C:\wlan.

FPGA Design Archive

The 802.11 FPGA Design is packaged as a .zip archive. When expanded the design has this folder structure:

<root>/
-ip_catalog/
    -mango/
    -adi/
-proj/
-src/
    -constr/
-tcl/

The <root> folder should have a short name consisting of only letters, numbers and simple punctuation, such as C:\work\wlan.

Creating the Vivado Project

The design archive includes a Tcl script which will construct a complete Vivado project. You must run this script once to create the Vivado project. After this you can re-open the project in the Vivado IDE to implement and iterate on the design.

You must create a folder for your project inside the proj folder. This new folder name is arbitrary (shorter is better) but must not contain spaces or special characters. The name may include version info. We’ll assume a project folder named wlan_proj_v0 below.

Warning

The Tcl script must be run in an empty folder. Do not run the script in a folder which already contains a Vivado project.

To create the Vivado project for the 802.11 hardware design:

  1. Launch the Vivado Tcl Shell: Start Menu ‣ Xilinx Design Tools ‣ Vivado 2024.2 ‣ Vivado 2024.2 Tcl Shell
  2. Change directory to your project folder: cd {c:/wlan/proj/wlan_proj_v0}
  3. Run the project creation script: source ../../tcl/wlan_top_PLATFORM_ARCH.tcl where PLATFORM and ARCH correspond to the desired hardware platform and FPGA design architecture. For example to create a project for the ZCU104, use script create_wlan_proj_zcu104.tcl.

The script assembles the complete Vivado project. The Tcl console will show extensive debug output, including many warnings which can be safely ignored.

If the script finishes successfully the Vivado GUI will launch and open the new project.

Exploring the Vivado Project

The Vivado GUI launches after the script finishes creating the project. You can use the GUI to explore the 802.11 hardware project, modify the hardware design, and implement the project for use on a development board.

You can close and re-open the project in Vivado. Do not re-run the Tcl script after the project is created.

The 802.11 reference design has a top-level IP Integrator (IPI) Block Diagram. The IPI design instantiates all IP cores, core properties, core connections, and connections to off-chip peripherals. Click Open Block Diagram in the Flow Navigator pane to open the IPI block diagram.

IP Integrator does not always preserve layout of block diagrams, so the initial block diagram may be quite cluttered. The Optimize Routing button will help. You can also rearrange blocks without affecting the hardware design.

Implement the FPGA Design

Implementing the design has four steps:

  1. Synthesis
  2. Implementation
  3. Bitstream Generation
  4. Export to SDK

You can launch each step individually if you want to explore the output of each step. For example to configure debug nets or update IO placement, you can run the Synthesis flow, then open the synthesized design.

To use the design in hardware you must run all four steps. Running “Generate Bitstream” will automatically run whatever Synthesis and Implementation processes are required. The final bitstream must then be exported to the SDK to build the complete 802.11 design.

The first Synthesis and Implementation runs will take a long time. Vivado caches implementation results so subsequent re-implementations will be much faster.

Export FPGA Design

After the hardware design is implemented the bitstream and hardware spec must be exported for use by the PetaLinux and SDK tools.

The PetaLinux and SDK tools import an archive from Vivado containing the FPGA bitstream, address map, and IP core software drivers. This archive is an XSA file.

To export the hardware archive from Vivado:

  1. Select File‣Export‣Bitstream
  2. In the Export dialog click Next, then check Include Bitstream, click Next, then leave Export To: set to the project directory.
  3. Find the wlan_top_wrapper.xsa file in the <vivado_proj_root>/ folder.

This XSA file must then be imported into the PetaLinux project for integration with the Linux environment and MAC software. Copy this XSA file to the PC running the PetaLinux tools, then refer to the PetaLinux Projects page.

Iterating on the Vivado Project

The process described above will create a new Vivado project. After creating the project you can modify the hardware design and re-implement the design iteratively using the standard Vivado flow.

The process for implementing a modified hardware design is the same as described above. You can run the Generate Bitstream at any point to re-implement the entire hardware design.

We strongly recommend incrementing version numbers of IP Cores when modifying the IP Core source. For example when modifying one of the PHY cores in System Generator, you should increment the IP Core version number in the System Generator settings before exporting the new core.

To update IP cores in the Vivado project:

  1. Open the Vivado IP Status report via Tools ‣ Report ‣ Report IP Status.
  2. There should be a link in the report’s title bar to Update IP Catalog. If so, click this. If not, run update_ip_catalog -rebuild in the Tcl console
  3. The IP Status Report will indicate which IP cores can be upgraded. Select the desired cores and click Upgrade Selected.

After the upgrade process completes review the hardware design for any required changes to IP core port connections or configuration. When the updated design is ready to implement, run Generate Bitstream, export the HDF file, then import the HDF file in your PetaLinux project.