6.2. PHY Receiver

The PHY Receiver IP core implements a complete, real-time waveform-to-bytes pipeline in FPGA fabric. The core is implemented in Xilinx System Generator.

Contents:

• PHY Receiver Interface
• PHY Receiver Register Map

Overview

The current 802.11 receiver core supports:

• 802.11a/b/g/n/ac/ax waveforms
• DSSS (1-2 Mbps rates)
• NONHT OFDM (all rates)
• HTMF 20MHz OFDM (MCS 0-7)
• VHT 20MHz SU OFDM (MCS 0-7)
• HE 20MHz SU OFDM (MCS 0-7)
• Better-than-spec Rx sensitivity on reference hardware

Fig. 6.2 Mango 802.11 Rx PHY block diagram