6.1. PHY Transmitter

The PHY Transmitter IP core implements a complete, real-time bytes-to-waveform pipeline in the FPGA fabric. The core is implemented in Xilinx System Generator.

Overview

The 802.11 transmitter core supports:

  • 802.11 b/a/g/n/ac/ax waveforms
    • DSSS (1Mbps)
    • NONHT OFDM (all rates)
    • HTMF 20MHz OFDM (MCS 0-7)
    • VHT 20MHz SU OFDM (MCS 0-7)
    • HE 20MHz SU OFDM (MCS 0-7)
  • Sample-accurate per-Tx timestamps
  • Selection diversity per transmission
  • Radio agnostic interface
  • Simple digital baseband (IQ) and control interface
  • Flexible sampling rate support
Mango 802.11 Tx PHY block diagram

Fig. 6.1 Mango 802.11 Tx PHY block diagram