6.1. PHY Transmitter

The PHY Transmitter IP core implements a complete, real-time bytes-to-waveform pipeline in the FPGA fabric. The core is implemented in Xilinx System Generator.

Contents:

• PHY Transmitter Interface
• PHY Transmitter Register Map

Overview

The 802.11 transmitter core supports:

• 802.11 b/a/g/n waveforms

  • DSSS (1MbpsS)
  • NONHT OFDM (all rates)
  • HTMF 20MHz OFDM (MCS 0-7)

• Sample-accurate per-Tx timestamps
• Selection diversity per transmission
• Radio agnostic interface
• Simple digital baseband (IQ) and control interface
• Flexible sampling rate support - up to 1/4 core clock frequency

Fig. 6.1 Mango 802.11 Tx PHY block diagram