PHY Transmitter Register Map¶

The PHY Transmitter IP core implements an AXI4-Lite slave interface which must be be connected to a CPU in the FPGA design. The software must configure and control the Tx PHY by accessing registers via this AXI interface.

The name and contents of each register are detailed below. The register address offsets are chosen automatically by System Generator when the IP core is exported. The actual address offsets are defined in the wlan_phy_tx_hw.h header file written by System Generator during the export process.

All software-accessible registers are 32 bits wide. Each register is either read/write (“Gateway In” block in the Sysgen model) or read-only (“Gateway Out” block).

Individual register fields have specific System Generator data types. Datatype descriptions below use the standard System Generator syntax, where UFixM_N and FixM_N refer to unsigned and signed fixed-point values with M total bits and binary point N.

Register List¶

Name	Access	Description
`FFT_CONFIG`	RW	FFT core configuration
`PHY_START_DELAY`	RW	Tx start delay configuration
`STATUS`	RO	Tx core status
`TXIQ_SCALE_DSSS`	RW	Digital scaling for DSSS waveforms
`TXIQ_SCALE_OFDM`	RW	Digital scaling for OFDM waveforms
`TX_CONFIG`	RW	Configuration bits

Register `FFT_CONFIG`¶

Name	Bits	Datatype	Description
`FFT_SCALING`	29:24	`UFix6_0`	Scaling configuration for FFT core, should be set to `0x2A`; refer to Xilinx FFT core datasheet for details on scaling modes
`CP_LEN`	15:8	`UFix8_0`	Number of cyclic prefix samples, must be set to `16`
`NUM_SC`	7:0	`UFix8_0`	Number of subcarriers, must be set to `64`

Register `PHY_START_DELAY`¶

Name	Bits	Datatype	Description
`PHY_START_DELAY`	13:0	`UFix14_0`	Sets delay between assertion of `TX_START.IND` by MAC core and start of Tx pipeline, in units of 4 `proc_clk` cycles

Register `STATUS`¶

Name	Bits	Datatype	Description
`DSSS_TX_RUNNING`	1	`UFix1_0`	Indicates Tx PHY DSSS pipeline is active; asserts when the MAC initiates a new transmission, de-asserts after last IQ sample is output
`DSSS_TX_RUNNING`	0	`UFix1_0`	Indicates Tx PHY DSSS pipeline is active; asserts when the MAC initiates a new transmission, de-asserts after last IQ sample is output

Register `TXIQ_SCALE_DSSS`¶

Name	Bits	Datatype	Description
`DSSS_Q_SCALE`	23:12	`Fix12_4`	Sets digital scaling at output of Tx DSSS pipeline for Q path
`DSSS_I_SCALE`	11:0	`Fix12_4`	Sets digital scaling at output of Tx DSSS pipeline for I path

Register `TXIQ_SCALE_OFDM`¶

Name	Bits	Datatype	Description
`OFDM_Q_SCALE`	23:12	`Fix12_4`	Sets digital scaling at output of Tx OFDM pipeline for Q path
`OFDM_I_SCALE`	11:0	`Fix12_4`	Sets digital scaling at output of Tx OFDM pipeline for I path

Register `TX_CONFIG`¶

Name	Bits	Datatype	Description
`USE_EXT_FIRSTLAST_SAMP`	1	`UFix1_0`	When de-asserted the Tx PHY ignores the `first_samp` and `last_samp` ports for generating the `tx_started` and `tx_done` signals to the MAC.