PHY Transmitter Interface¶

The PHY Transmitter IP core must be instantiated in the FPGA design along with other required cores. The PHY Tx core also requires a CPU in the FPGA design for configuration and control from software.

The MAC Core provides configuration and data for each packet transmission. The PHY Transmitter consumes the configuration/data and emits a digital IQ waveform for transmission by the radio. An external core is typically required to connect the Tx PHY IQ stream to the radio DAC interfaces. Mango provides the wlan_phy_tx_iq_cdc core in reference projects targeting the AD9361 radio.

The PHY Transmitter core port are described below.

Clocks and Resets¶

The Tx PHY core operates in a single clock domain. The current PHY design requires the clock be at least 4x the sampling frequency. Mango reference projects use a 160MHz clock for 20MSps sample rate.

Port	Direction	Data Type	Description
`clk`	Input	`UFix1_0`	Processing clock input, must be at least 4x faster than the sampling rate (toggling rate of `rf_tx_iq_rd_en` input)
`wlan_phy_tx_aresetn`	Input	`UFix1_0`	Asynchronous active-low reset for AXI interface logic. This reset does not clear registers in the AXI slave interface. This signal should be connected to the same reset as the AXI infrastructure cores.

AXI Memory Mapped Slave Interface¶

The Tx PHY IP core implements an AXI4-Lite slave interface with configuration and status registers. The FPGA design must connect this AXI slave interface to an AXI master, typically a CPU. The CPU must configure the Tx PHY IP core at boot by writing the core’s registers.

The Tx core’s AXI interface appears as a bus named wlan_phy_tx_regs_s_axi in the Vivado tools. This bus interface wraps all the inputs/outputs which implement the AXI interface.

AXI Stream Slave Interfaces¶

The Tx PHY IP core implements two AXI Stream slave interfaces. Both interfaces are driven by the MAC core.

Interface	Direction	Data Width	Description
`s_axis_tx_wvfm_cfg`	Slave	`64`	Waveform config from MAC core, asserted for 1 beat per packet transmission. MAC core must provide valid MAC payload data on the `s_axis_pkt_data` stream immediately after writing a waveform configuration on this stream. The Tx PHY will consume the number of bytes specified in the waveform configuration’s length fields on the `s_axis_pkt_data` before resetting and waiting a new waveform configuration word.
`s_axis_pkt_data`	Slave	`8`	Byte stream of MAC payload for packet transmission. Waveform format is defined by most recent `s_axis_tx_wvfm_cfg` word. MAC core must provide the number of bytes specified in the waveform configuration and must assert `tlast` on the final MAC payload byte.

MAC Support Core Interface¶

The following ports must be connected to the MAC Core (wlan_mac_hw) in the FPGA design. The MAC uses these signals to update medium state at the start and end of the waveform transmission.

Port	Direction	Data Type	Description
`phy_tx_started`	Output	`UFix1_0`	Asserts when first sample is output from Tx PHY to DACs
`phy_tx_done`	Output	`UFix1_0`	Pulses high after last sample is output from Tx PHY to DACs

I/Q Sample Interfaces¶

The Tx PHY emits a waveform as digital IQ on an AXI Stream master interface. This stream must be connected to an interface core in the FPGA design. The interface core handles any clock domain crossing between the Tx PHY and radio logic, and adapts the generic IQ stream format to the radio’s IQ format.

Interface	Direction	Data Width	Description
`m_axis_tx_iq`	Master	`64`	Digital IQ stream, each 64-bit word contains two IQ samples (one per radio interface, labeled RF A and RF B). Each IQ sample is 32 bits (16 bits each for I and Q). This interface does not support back pressure. The connected slave must implement a FIFO if the downstream logic requires any buffering.

The Tx PHY also provides the following ports to facilitate radio control and accurate waveform timing.

Port	Direction	Data Type	Description
`rf_tx_first_samp`	Input	`UFix1_0`	Must assert for one cycle when the first sample of a waveform has been output to the radio, reflecting any latency between the Tx PHY and RF frontend.
`rf_tx_last_samp`	Input	`UFix1_0`	Must assert for one cycle when the last sample of a waveform has been output to the radio, reflecting any latency between the Tx PHY and RF frontend.
`iq_intf_reset`	Output	`UFix1_0`	Reset output from the PHY to clear state and stale IQ in external interface logic when the Tx PHY itself is reset.
`rc_usr_txen_a`	Output	`UFix1_0`	Asserts high when Tx PHY is providing a waveform for the RF A interface.
`rc_usr_txen_b`	Output	`UFix1_0`	Asserts high when Tx PHY is providing a waveform for the RF B interface.
`rc_usr_txen_any`	Output	`UFix1_0`	Asserts high when Tx PHY is providing a waveform for any RF interface.
`block_rx_iq`	Output	`UFix1_0`	Asserts high when Tx PHY is outputting any waveform, can be used to block IQ inputs at Rx PHY to avoid attempted reception of local transmission.