PHY Receiver Interface¶
The PHY Receiver IP core must be instantiated in the FPGA design along with other required cores. The PHY Rx core also requires a CPU in the FPGA design for configuration and control from software.
The PHY Receiver core port are described below.
Clocks and Resets¶
The Rx PHY core has a single clock domain that must be synchronous to the IQ sample stream. Any clock domain crossing logic must be implemented outside the Rx PHY core. In Mango reference designs with ADI radios the clock domain cross is implemented in the wlan_phy_rx_iq_cdc utility core.
| Port | Direction | Data Type | Description |
|---|---|---|---|
clk |
Input | UFix1_0 |
Clock input, must be synchronous to and at least 4x faster than the IQ sampling rate. Typically this is connected to a 160MHz clock that is synchronized to the radio reference clock. |
wlan_phy_rx_aresetn |
Input | UFix1_0 |
Asynchronous active-low reset for AXI interface logic. This reset does not clear registers in the AXI slave interface. This signal should be connected to the same reset as the AXI infrastructure cores. |
AXI Memory Mapped Slave Interface¶
The Rx PHY IP core implements an AXI4-Lite slave interface with many configuration and status registers. The FPGA design must connect this AXI slave interface to an AXI master, typically an AXI interconnect and CPU. The CPU must configure the Rx PHY IP core at boot by writing the core’s registers.
The Rx core’s AXI interface appears as a bus named wlan_phy_rx_regs_s_axi in the Vivado tools. This bus interface wraps all the inputs/outputs which implement the AXI interface.
AXI Stream Master Interfaces¶
The Rx PHY IP core uses multiple AXI Stream master interfaces to write metadata and paylaods for received waveforms. These streams connect to the MAC Core for further processing and reporting to the driver.
| Interface | Direction | Data Width | Description |
|---|---|---|---|
m_axis_rx_data |
Master | 8 |
Decoded MAC payload bytes, final byte of each waveform is marked with tlast. |
m_axis_phy_hdr_rx |
Master | 64 |
PHY header fields (PHY mode, MCS, Length, Aggregate, Short GI, etc.) decoded from newly received waveform; this stream writes one word per waveform before first payload byte is written to m_axis_rx_data. |
m_axis_wvfm_info |
Master | 64 |
Waveform metadata (Rx power, Antenna selection, AGC gain selection, etc.); this stream writes one word per waveform before first payload byte is written to m_axis_rx_data. |
MAC Core Interface¶
The following ports must be connected to the MAC Core (wlan_mac_hw) in the FPGA design.
| Port | Direction | Data Type | Description |
|---|---|---|---|
phy_rx_block_pktdet |
Input | UFix1_0 |
When asserted blocks any new receptions, does not interrupt ongoing reception. Asserted by MAC hardware to ensure a reception is not overwritten before it is processed by software. |
phy_cca_ind_busy |
Output | UFix1_0 |
Indicates Rx PHY observes a busy medium, connected to MAC hardware’s CCA logic. |
phy_rx_start_ind |
Output | UFix1_0 |
Asserts when Rx PHY has started receiving a new packet |
phy_rx_end_ind |
Output | UFix1_0 |
Asserts at MAC’s RX_END event (extension period after last sample on medium) |
phy_rx_end_rxerror |
Output | UFix2_0 |
Asserts when an Rx event ends with an error, typically a decoding error in the PHY header |
IQ Sample Interface¶
The following ports must be connected to the radio interface in the FPGA design.
| Port | Direction | Data Type | Description |
|---|---|---|---|
rf_X_iq_valid |
Inputs | UFix1_0 |
Indicates signals on rf_X_<i,q> are valid, maximum rate is 1/4 of the clk input |
rf_a_<i,q> |
Inputs | Fix16_15 |
Complex baseband (IQ) samples from RF A interface |
rf_b_<i,q> |
Inputs | Fix16_15 |
Complex baseband (IQ) samples from RF B interface |
rf_gain_index |
Inputs | UFix7_0 |
Gain index provided by radio or RF frontend; format depends on hardware platform |
Debug Signals¶
The Rx PHY connects many internal signals to top-level ports identified by the dbg_ prefix. These ports can be routed to top-level FPGA pins or on-chip ILA cores for easier debugging in hardware. The selection of ports varies with Rx PHY core version.