UART Setup¶
Both CPUs in 802.11 design can print to UART. CPU High also accepts UART input. The 802.11 FPGA design provides various options for connecting UART interfaces to each CPU.
UART Interfaces¶
RFSOM carriers have single USB-UART interface routed to a micro USB jack. This USB-UART interface is connected to pins for a UARTPS peripheral in the Zynq PS. The 802.11 FPGA design maps this UARTPS peripheral into the address space of both CPU High and CPU Low.
The FMC Carrier USB-UART transceiver is Silicon Labs CP2103. This transceiver requires the Silicon Labs Virtual COM Port (VCP) driver. If your OS does not include this driver you can download it from https://www.silabs.com/products/development-tools/software/usb-to-uart-bridge-vcp-drivers.
The RFSOM FMC carrier also implements a PMOD header. The 802.11 FPGA design supports connecting a second USB-UART interface to the PMOD header using the Digilent USBUART PMOD module. The USBUART module must be connected to the top row of the PMOD header with the top of the PMOD module facing upwards.
The Digilent USBUART module uses an FTDI USB-UART transceiver which requires the FTDI VCP driver. If your OS does not include this driver you can download it from http://www.ftdichip.com/Drivers/VCP.htm.
Connecting CPUs to UARTs¶
The SDK BSP for each CPU configures which UART peripheral is used for stdin/stdout.
CPU High supports:
ps7_uart_1(default): connects CPU to carrier USB-UART interfacenone: disables UART I/O
CPU Low supports:
mb_low_periphs_mb_low_uart(default): connects CPU to PMOD header USB-UART interfaceps7_uart_1: connects CPU to carrier USB-UART interfacenone: disables UART I/O
The SDK supports connecting both CPUs to the same UART. This configuration will interleave output from both CPUs.
The BSP must be rebuilt after changing the stdin/stdout assignment in the BSP settings. Right-click the BSP project in the Project Explorer tab and select Re-generate BSP Sources.
Terminal Configuration¶
Any serial terminal can be used with the USB-UART interfaces. Putty is a good option.
You can use Device Manager (or your OS’s equivalent) to identify which COM port number is assigned to each USB-UART interface. In our experience Windows consistently assigns the same COM port number to a given board.
The 802.11 FPGA Design configures both UART peripherals for:
| Param | Value |
|---|---|
| Speed | 115200 bps |
| Data bits | 8 |
| Stop bits | 1 |
| Parity | None |
| Flow Control | XON/XOFF |
We also recommend enabling “Implicit CR in every LF” and “Implicit LF in every CR” in the terminal settings. This will improve the readability of the UART output in the reference MAC code.