GPIO¶
The ZCU104 implements two PMOD ports each with 8 pins routed to FPGA I/O.
The 802.11 MAC/PHY design uses the GPIO port for debug I/O. The GPIO pins are connected to the wlan_hw_controller core which implements the necessary logic to use each GPIO pin as an input or output. The wlan_hw_controller core supports reading GPIO inputs from software or hardware, and supports setting GPIO outputs from software or hardware. By default the 16 GPIO pins are configured as software-controlled outputs.
Pinout¶
The Mango 802.11 design uses the PMOD pins as general purpose I/O. No PMOD module is requied to use these pins.
The figure below shows the mapping of PMOD header pins to signals in the 16-bit GPIO signal in the FPGA design. GPIO are mapped to PMOD headers PMOD 0 (J55) and PMOD 1 (J87).
Fig. 2.2 ZCU104 PMOD / GPIO mapping
Each PMOD header has two 3.3v power pins and two Ground pins. The GPIO are 3.3v logic signals.
802.11 Debug Outputs¶
The 802.11 MAC/PHY design drives real-time MAC and PHY status signals to debug outputs. On hardware platforms with debug headers these status outputs can be probed with an oscillosope to observe MAC/PHY state in real-time.
The reference 802.11 FPGA design for ZCU104 connects 16 MAC/PHY debug signals to GPIO. Observing these signals with a scope requires external equipment to access the GPIO pins.
| GPIO | Signal | Description |
|---|---|---|
| 0 | PHY Rx: payload |
High when OFDM Rx is receiving a packet |
| 1 | PHY Rx: dsss_rx_active |
High when DSSS Rx is receiving a packet |
| 2 | PHY Rx: fcs_good |
Pulses high when Rx has FCS Good result |
| 3 | PHY Rx: lts_sync |
Pulses high on OFDM LTS preamble sync |
| 4 | PHY Rx: pkt_det_dsss |
High when DSSS Rx has detected packet |
| 5 | PHY Rx: pkt_det_ofdm |
High when OFDM Rx has detected packet |
| 6 | PHY Rx: lts_timeout |
Pulses high when OFDM Rx terminates after no LTS sync |
| 7 | PHY Tx: tx_active |
High when Tx PHY is transmitting a packet |
| 8 | MAC: idle_for_difs |
High when MAC observes CCA IDLE for >T_DIFS |
| 9 | MAC: nav_active |
High when MAC NAV is nonzero |
| 10 | MAC: tx_a_pending |
High when Tx is pending from Tx Controller A |
| 11 | MAC: tx_a_backoff_active |
High when Tx Controller A backoff counter is nonzero |
| 12 | MAC: tx_b_pending |
High when Tx is pending from Tx Controller B |
| 13 | MAC: tx_c_pending |
High when Tx is pending from Tx Controller C |
| 14 | MAC: tx_c_backoff_active |
High when Tx Controller C backoff counter is nonzero |
| 15 | MAC: tx_d_pending |
High when Tx is pending from Tx Controller D |