The MAC IP Core includes various timers. These timers are implemented in the FPGA fabric to ensure real-time operation without software monitoring. These timers start and expire automatically. The MAC software can use these timers to implement medium access timing relative to transmissions, receptions, and other medium activity.

All timer parameters are configured from the MAC software. These timers support our reference DCF implementation. They can also be reconfigured for arbitrary MAC protocols with custom MAC software.

Post Tx/Rx Timers

The Post Tx/Rx timers are counters in the FPGA fabric which start immediately after every Tx/Rx event. These timers are connected to the Transmit Controller state machines to implement precise sequencing of Tx/Rx events. For example a Post Rx timer is used to implement the SIFS interval between a data reception and ACK transmission, and a Post Tx timer is used to implement the timeout interval following an unacknowledged data transmission.


The DIFS/EIFS timers increment during periods of no medium activity. MAC protocols use these timers to defer new transmissions following medium activity. The DIFS/EIFS timers are connected to the Tx controller state machines and can be used or ignored by custom MAC protocols.