MAC Core Register Map¶
The MAC core implements an AXI4-Lite slave interface which must be be connected to a CPU in the FPGA design. The software must configure and control the MAC core by accessing registers via this AXI interface.
The name and contents of each register are detailed below. The register address offsets are chosen automatically by System Generator when the IP core is exported. The actual address offsets are defined in the wlan_mac_hw_hw.h
header file written by System Generator during the export process.
All software-accessible registers are 32 bits wide. Each register is either read/write (“Gateway In” block in the Sysgen model) or read-only (“Gateway Out” block).
Individual register fields have specific System Generator data types. Datatype descriptions below use the standard System Generator syntax, where UFixM_N
and FixM_N
refer to unsigned and signed fixed-point values with M
total bits and binary point N
.
Register List¶
Name | Access | Description |
---|---|---|
BACKOFF_CTRL |
RW | Software control for Tx A backoff counter |
CALIB_TIMES |
RW | Calibrated IFS values |
CONTROL |
RW | Control register |
CURR_BYTE_INDEXES |
RO | Byte indexes for current waveform |
CURR_WVFM_PARAMS |
RO | PHY params for waveform currently being received by MAC/PHY |
CURR_WVFM_SUBFRAME_INDEXES |
RO | Current waveform indices |
FIRST_TBTT_TU |
RW | First TBTT TU Value |
IFS_INTERVALS1 |
RW | Inter-frame space (IFS) values (reg 1) |
IFS_INTERVALS2 |
RW | Inter-frame space (IFS) values (reg 2) |
INTR_A_<STATUS,CLR,EN> |
RW | Interrupt A Status/Clear/Enable Bits |
INTR_B_<STATUS,CLR,EN> |
RW | Interrupt B Status/Clear/Enable Bits |
MAC_RX_PROC_CFG |
RW | Config for MAC Rx logic |
MAC_RX_PROC_LEN_QUANT_THRESH01 |
RW | MPDU Length Quantizer Thresholds |
NAV_CTRL |
RW | NAV logic config and control |
NAV_VALUE |
RO | Current NAV value (100 nsec units) |
PKT_DROP_COUNTS0 |
RO | Packet drop counts |
PKT_DROP_COUNTS1 |
RO | Packet drop counts |
PKT_DROP_COUNTS2 |
RO | Packet drop counts |
POST_RX_TIMERS |
RW | Post-Rx timers configuraiton |
POST_TX_TIMERS |
RW | Post-Tx timers configuraiton |
RX_ADDR1_MATCH_B0 |
RW | MAC Header addr1 Matching - Byte 0 |
RX_ADDR1_MATCH_B1 |
RW | MAC Header addr1 Matching - Byte 1 |
RX_ADDR1_MATCH_B2 |
RW | MAC Header addr1 Matching - Byte 2 |
RX_ADDR1_MATCH_B3 |
RW | MAC Header addr1 Matching - Byte 3 |
RX_ADDR1_MATCH_B4 |
RW | MAC Header addr1 Matching - Byte 4 |
RX_ADDR1_MATCH_B5 |
RW | MAC Header addr1 Matching - Byte 5 |
RX_BYTE_DROP_STATS |
RO | Dropped byte counts |
RX_DMA_CTRL_STATUS |
RO | Status values from Rx DMA control logic |
RX_DMA_FIFO_STATS |
RO | Status values for pre-DMA FIFO |
RX_FILT_CFG |
RW | Config for filtering Rx before DMA |
RX_TIMESTAMP_MSB |
RO | Rx start MAC time - 32 LSB |
RX_TIMESTAMP_MSB |
RO | Rx start MAC time - 32 MSB |
STATUS |
RO | MAC core status register |
SW_RX_METADATA_0 |
RW | Software-provided metadata included in Rx reports |
TBTT_INTVL |
RW | TBTT Interval Targets |
TXRX_START_TIMESTAMPS_FRAC |
RO | Fractional MAC time captured at last TX_START / RX_START |
TX_A_BACKOFF_COUNTER |
RO | Current backoff counter A value |
TX_CD_BACKOFF_COUNTERS |
RO | Current backoff counters C and D values |
TX_CTRL_A_PARAMS |
RW | Tx Controller A configuration |
TX_CTRL_B_PARAMS |
RW | Tx Controller B configuration |
TX_CTRL_C_PARAMS |
RW | Tx Controller C configuration |
TX_CTRL_D_PARAMS |
RW | Tx Controller D configuration |
TX_CTRL_STATUS |
RO | Tx controllers status register |
TX_PKT_BUF_SEL |
RW | Packet buffer selection and interface config |
TX_START |
RW | Tx controllers start triggers |
TX_TIMESTAMP_MSB |
RO | TX start MAC time - 32 LSB |
TX_TIMESTAMP_MSB |
RO | TX start MAC time - 32 MSB |
TX_WVFM_CFG_L |
RW | 32 LSB of Tx waveform config |
TX_WVFM_CFG_M |
RW | 32 MSB of Tx waveform config |
Register BACKOFF_CTRL
¶
Name | Bits | Datatype | Description |
---|---|---|---|
BACKOFF_START |
31 | UFix1_0 |
Start Tx A backoff |
NUM_SLOTS |
15:0 | UFix16_0 |
Number of slots |
Register CALIB_TIMES
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_DIFS |
9:0 | UFix10_0 |
Calibrated TX_DIFS interval |
Register CONTROL
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_PREFETCH_DLY |
27:25 | UFix3_0 |
Sets the delay from TX_START to retrieving the first byte from the Tx pkt buffer |
RESET_TX_PHY_ACTIVE |
24 | UFix1_0 |
Resets the Tx PHY Active latches |
RESET_RX_PHY_ACTIVE |
23 | UFix1_0 |
Resets the Rx PHY Active latches |
EN_TBTT |
22 | UFix1_0 |
Enables TBTT interrupt generation logic |
PAUSE_TX_CTRL_D |
20 | UFix1_0 |
Pauses Tx Controller D |
PAUSE_TX_CTRL_C |
19 | UFix1_0 |
Pauses Tx Controller C |
PAUSE_TX_CTRL_A |
18 | UFix1_0 |
Pauses Tx Controller A |
RESET_BACKOFF_D |
17 | UFix1_0 |
Resets backoff counter for Tx Controller D |
RESET_BACKOFF_C |
16 | UFix1_0 |
Resets backoff counter for Tx Controller C |
RESET_BACKOFF_A |
15 | UFix1_0 |
Resets backoff counter for Tx Controller A |
RESET_TX_CTRL_D |
14 | UFix1_0 |
Resets Tx Controller D |
RESET_TX_CTRL_C |
13 | UFix1_0 |
Resets Tx Controller C |
RESET_TX_CTRL_B |
12 | UFix1_0 |
Resets Tx Controller B |
RESET_TX_CTRL_A |
11 | UFix1_0 |
Resets Tx Controller A |
RESET_RX_STARTED |
10 | UFix1_0 |
Resets the RX_START latch |
CCA_FORCE_BUSY |
8 | UFix1_0 |
Holds CCA.BUSY high independent of medium activity |
CCA_IGNORE_NAV |
7 | UFix1_0 |
Disables the NAV -> CCA.BUSY path |
CCA_IGNORE_TX_PHY |
6 | UFix1_0 |
Disables the Tx PHY -> CCA.BUSY path |
CCA_IGNORE_RX_PHY |
5 | UFix1_0 |
Disables the Rx PHY -> CCA.BUSY path |
DISABLE_NAV |
1 | UFix1_0 |
Disables the NAV logic |
RESET |
0 | UFix1_0 |
Gloabl MAC core reset |
Register CURR_BYTE_INDEXES
¶
Name | Bits | Datatype | Description |
---|---|---|---|
MPDU_BYTE_INDEX |
31:16 | UFix16_0 |
Byte index of current subframe |
WVFM_BYTE_INDEX |
15:0 | UFix16_0 |
Waveform byte index (0 is first byte in overall MAC payload) |
Register CURR_WVFM_PARAMS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
MCS |
27:20 | UFix8_0 |
MCS of current waveform |
AGG |
19 | UFix1_0 |
AGGREGATE field for current waveform |
PHY_MODE |
18:16 | UFix3_0 |
PHY Mode of current waveform |
LENGTH |
15:0 | UFix16_0 |
Number of bytes in current waveform |
Register CURR_WVFM_SUBFRAME_INDEXES
¶
Name | Bits | Datatype | Description |
---|---|---|---|
SUBFRAME_IDX |
29:24 | UFix6_0 |
Current subframe index |
WVFM_IDX |
23:0 | UFix24_0 |
24 LSB of waveform index for most recent Rx |
Register FIRST_TBTT_TU
¶
Name | Bits | Datatype | Description |
---|---|---|---|
FIRST_TBTT_TU |
31:0 | UFix32_0 |
Absolute TU value for first TBTT event |
Register IFS_INTERVALS1
¶
Name | Bits | Datatype | Description |
---|---|---|---|
DIFS |
29:20 | UFix10_0 |
DIFS duration, 100nsec units |
SLOT |
9:0 | UFix10_0 |
Slot duration, 100nsec units |
Register IFS_INTERVALS2
¶
Name | Bits | Datatype | Description |
---|---|---|---|
EIFS |
15:0 | UFix16_0 |
EIFS duration, 100nsec units |
Register INTR_A_<STATUS,CLR,EN>
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_D_DONE |
11 | UFix1_0 |
Tx Controller D Done |
TX_C_DONE |
10 | UFix1_0 |
Tx Controller C Done |
TX_B_DONE |
9 | UFix1_0 |
Tx Controller B Done |
TX_A_DONE |
8 | UFix1_0 |
Tx Controller A Done |
TX_D_PHY_START |
7 | UFix1_0 |
Tx Controller D Started PHY |
TX_C_PHY_START |
6 | UFix1_0 |
Tx Controller C Started PHY |
TX_B_PHY_START |
5 | UFix1_0 |
Tx Controller B Started PHY |
TX_A_PHY_START |
4 | UFix1_0 |
Tx Controller A Started PHY |
TBTT_TARGET_1 |
3 | UFix1_0 |
TBTT Target 1 triggered |
TBTT_TARGET_0 |
2 | UFix1_0 |
TBTT Target 0 triggered |
TX_PHY_STARTED |
1 | UFix1_0 |
Tx PHY started |
TX_A_TIMEOUT |
0 | UFix1_0 |
Tx Controller A finished in timeout |
Register INTR_B_<STATUS,CLR,EN>
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TBTT_TARGET_1 |
3 | UFix1_0 |
TBTT Target 1 triggered |
TBTT_TARGET_0 |
2 | UFix1_0 |
TBTT Target 0 triggered |
Register MAC_RX_PROC_CFG
¶
Name | Bits | Datatype | Description |
---|---|---|---|
RX_PROC_RESET |
31 | UFix1_0 |
Resets MAC core Rx processing logic |
BLOCK_RX_PHY |
30 | UFix1_0 |
Prevents new waveform detections in Rx PHY, blocks Rx after current waveform |
RX_DMA_CTRL_EN |
29 | UFix1_0 |
Enables submitting transfers to the Rx DMA |
MAC_HDR_RX_FIFO_EN |
28 | UFix1_0 |
Enables writing words to the MAC Header Rx FIFO |
DMA_CMD_MAX_LEN |
15:12 | UFix4_0 |
Maximum allowed value for DMA command LENGTH field, units of 512 bytes |
SUPPRESS_ADDR1_MISMATCH |
11 | UFix1_0 |
Suppresses reporting events without an ADDR1 match |
SUPPRESS_WVFM_END |
10 | UFix1_0 |
Suppresses reporting of WVFM_END events |
SUPPRESS_HDR_RX |
9 | UFix1_0 |
Suppresses reporting of MAC_HDR_RX events |
AMPDU_MIN_LENGTH |
8:4 | UFix5_0 |
Minimum value for AMPDU delimiter length field to process a subframe |
MAC_HDR_BUF_OFFSET |
2:0 | UFix3_0 |
Offset into MAC Header BRAM, units of 512 bytes |
Register MAC_RX_PROC_LEN_QUANT_THRESH01
¶
Name | Bits | Datatype | Description |
---|---|---|---|
THRESH2 |
31:8 | UFix24_0 |
Length threshold 0, units of 32 bytes |
THRESH0 |
7:4 | UFix4_0 |
Length threshold 0, units of 32 bytes |
THRESH0 |
3:0 | UFix4_0 |
Length threshold 0, units of 8 bytes |
Register PKT_DROP_COUNTS0
¶
Name | Bits | Datatype | Description |
---|---|---|---|
BAD_FCS |
31:16 | UFix16_0 |
Number of pkts dropped by bad FCS filter |
TYPE_CTRL |
15:0 | UFix16_0 |
Number of pkts dropped by Control type filter |
Register PKT_DROP_COUNTS1
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TOO_LONG |
31:16 | UFix16_0 |
Number of pkts dropped for being too long |
TOO_SHORT |
15:0 | UFix16_0 |
Number of pkts dropped for being too short |
Register PKT_DROP_COUNTS2
¶
Name | Bits | Datatype | Description |
---|---|---|---|
ADDR1_MISMATCH |
15:0 | UFix16_0 |
Number of pkts dropped by ADDR1 fiters |
Register POST_RX_TIMERS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
POST_RX_TIMER2_EN |
31 | UFix1_0 |
Enables Post-Rx Timer #2 |
POST_RX_TIMER2_COUNTTO |
30:16 | UFix15_0 |
Post-Rx Timer #2 count-to value |
POST_RX_TIMER1_EN |
15 | UFix1_0 |
Enables Post-Rx Timer #1 |
POST_RX_TIMER1_COUNTTO |
14:0 | UFix15_0 |
Post-Rx Timer #1 count-to value |
Register POST_TX_TIMERS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
POST_TX_TIMER2_EN |
31 | UFix1_0 |
Enables Post-Tx Timer #2 |
POST_TX_TIMER2_COUNTTO |
30:16 | UFix15_0 |
Post-Tx Timer #2 count-to value |
POST_TX_TIMER1_EN |
15 | UFix1_0 |
Enables Post-Tx Timer #1 |
POST_TX_TIMER1_COUNTTO |
14:0 | UFix15_0 |
Post-Tx Timer #1 count-to value |
Register RX_ADDR1_MATCH_B0
¶
Name | Bits | Datatype | Description |
---|---|---|---|
ADDR1_3_B0 |
31:24 | UFix8_0 |
Byte 0 for ADDR1 Match 3 |
ADDR1_2_B0 |
23:16 | UFix8_0 |
Byte 0 for ADDR1 Match 2 |
ADDR1_1_B0 |
15:8 | UFix8_0 |
Byte 0 for ADDR1 Match 1 |
ADDR1_0_B0 |
7:0 | UFix8_0 |
Byte 0 for ADDR1 Match 0 |
Register RX_ADDR1_MATCH_B1
¶
Name | Bits | Datatype | Description |
---|---|---|---|
ADDR1_3_B1 |
31:24 | UFix8_0 |
Byte 1 for ADDR1 Match 3 |
ADDR1_2_B1 |
23:16 | UFix8_0 |
Byte 1 for ADDR1 Match 2 |
ADDR1_1_B1 |
15:8 | UFix8_0 |
Byte 1 for ADDR1 Match 1 |
ADDR1_0_B1 |
7:0 | UFix8_0 |
Byte 1 for ADDR1 Match 0 |
Register RX_ADDR1_MATCH_B2
¶
Name | Bits | Datatype | Description |
---|---|---|---|
ADDR1_3_B2 |
31:24 | UFix8_0 |
Byte 2 for ADDR1 Match 3 |
ADDR1_2_B2 |
23:16 | UFix8_0 |
Byte 2 for ADDR1 Match 2 |
ADDR1_1_B2 |
15:8 | UFix8_0 |
Byte 2 for ADDR1 Match 1 |
ADDR1_0_B2 |
7:0 | UFix8_0 |
Byte 2 for ADDR1 Match 0 |
Register RX_ADDR1_MATCH_B3
¶
Name | Bits | Datatype | Description |
---|---|---|---|
ADDR1_3_B3 |
31:24 | UFix8_0 |
Byte 3 for ADDR1 Match 3 |
ADDR1_2_B3 |
23:16 | UFix8_0 |
Byte 3 for ADDR1 Match 2 |
ADDR1_1_B3 |
15:8 | UFix8_0 |
Byte 3 for ADDR1 Match 1 |
ADDR1_0_B3 |
7:0 | UFix8_0 |
Byte 3 for ADDR1 Match 0 |
Register RX_ADDR1_MATCH_B4
¶
Name | Bits | Datatype | Description |
---|---|---|---|
ADDR1_3_B4 |
31:24 | UFix8_0 |
Byte 4 for ADDR1 Match 3 |
ADDR1_2_B4 |
23:16 | UFix8_0 |
Byte 4 for ADDR1 Match 2 |
ADDR1_1_B4 |
15:8 | UFix8_0 |
Byte 4 for ADDR1 Match 1 |
ADDR1_0_B4 |
7:0 | UFix8_0 |
Byte 4 for ADDR1 Match 0 |
Register RX_ADDR1_MATCH_B5
¶
Name | Bits | Datatype | Description |
---|---|---|---|
ADDR1_3_B5 |
31:24 | UFix8_0 |
Byte 5 for ADDR1 Match 3 |
ADDR1_2_B5 |
23:16 | UFix8_0 |
Byte 5 for ADDR1 Match 2 |
ADDR1_1_B5 |
15:8 | UFix8_0 |
Byte 5 for ADDR1 Match 1 |
ADDR1_0_B5 |
7:0 | UFix8_0 |
Byte 5 for ADDR1 Match 0 |
Register RX_BYTE_DROP_STATS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
HDR_WORDS_DROPPED |
31:16 | UFix16_0 |
Number of MAC Header Rx words dropped by FIFO |
DMA_FIFO_DROPPED_BYTES |
15:0 | UFix16_0 |
Number of bytes dropped by pre-DMA FIFO |
Register RX_DMA_CTRL_STATUS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
DROPPED_DMA_CMDS |
31:16 | UFix16_0 |
Number of DMA commands dropped due to DMA being too busy |
DROPPED_RX_NO_BUF |
15:0 | UFix16_0 |
Number of Rx packets dropped before DMA due to buffer underflow |
Register RX_DMA_FIFO_STATS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
MAX_OCC |
31:16 | UFix16_0 |
Maximum FIFO occupancy in bytes |
CURR_OCC |
15:0 | UFix16_0 |
Current FIFO occupancy in bytes |
Register RX_FILT_CFG
¶
Name | Bits | Datatype | Description |
---|---|---|---|
DROP_ADDR1_MISMATCH |
2 | UFix1_0 |
Drop packets which do not match one of the ADDR1 values |
DROP_CTRL_PKTS |
1 | UFix1_0 |
Drop control packets |
DROP_BAD_FCS |
0 | UFix1_0 |
Drop bad FCS packets |
Register RX_TIMESTAMP_MSB
¶
Name | Bits | Datatype | Description |
---|---|---|---|
RX_TIMESTAMP_LSB |
31:0 | UFix32_0 |
32 LSB of 64-bit MAC time at last RX_START |
Register RX_TIMESTAMP_MSB
¶
Name | Bits | Datatype | Description |
---|---|---|---|
RX_TIMESTAMP_MSB |
31:0 | UFix32_0 |
32 MSB of 64-bit MAC time at last RX_START |
Register STATUS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
CCA_BUSY |
16 | UFix1_0 |
CCA indicates busy medium |
NAV_BUSY |
15 | UFix1_0 |
NAV counter is nonzero |
RX_END_ERROR |
13:12 | UFix2_0 |
Erorr code for RX_END |
RX_PHY_STARTED |
10 | UFix1_0 |
Rx PHY started latch |
RX_PHY_ACTIVE |
9 | UFix1_0 |
Rx PHY is active |
TX_PHY_ACTIVE |
8 | UFix1_0 |
Tx PHY is active |
TX_D_DONE |
7 | UFix1_0 |
Tx controller D is done |
TX_D_PENDING |
6 | UFix1_0 |
Tx controller D is running |
TX_C_DONE |
5 | UFix1_0 |
Tx controller C is done |
TX_C_PENDING |
4 | UFix1_0 |
Tx controller C is running |
TX_B_DONE |
3 | UFix1_0 |
Tx controller B is done |
TX_B_PENDING |
2 | UFix1_0 |
Tx controller B is running |
TX_A_DONE |
1 | UFix1_0 |
Tx controller A is done |
TX_A_PENDING |
0 | UFix1_0 |
Tx controller A is running |
Register SW_RX_METADATA_0
¶
Name | Bits | Datatype | Description |
---|---|---|---|
SW_RX_PARAMS |
31:0 | UFix32_0 |
Software-set value copied into all Rx MAC Header reports |
Register TBTT_INTVL
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TBTT_INTVL |
29:20 | UFix10_0 |
TBTT Interval in TU |
TBTT_TARGET1 |
19:10 | UFix10_0 |
TU Target for TBTT Target 1 event |
TBTT_TARGET0 |
9:0 | UFix10_0 |
TU Target for TBTT Target 0 event |
Register TXRX_START_TIMESTAMPS_FRAC
¶
Name | Bits | Datatype | Description |
---|---|---|---|
RX_START_TIMESTAMP_FRAC |
19:10 | UFix10_0 |
10-bit fractional MAC time at last RX_START |
TX_START_TIMESTAMP_FRAC |
9:0 | UFix10_0 |
10-bit fractional MAC time at last TX_START |
Register TX_A_BACKOFF_COUNTER
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_A_BACKOFF_COUNT |
15:0 | UFix16_0 |
Current backoff counter A value |
Register TX_CD_BACKOFF_COUNTERS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_D_BACKOFF_COUNT |
31:16 | UFix16_0 |
Current backoff counter D value |
TX_C_BACKOFF_COUNT |
15:0 | UFix16_0 |
Current backoff counter C value |
Register TX_CTRL_A_PARAMS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
POST_WAIT_POST_TX_TIMER_2 |
26 | UFix1_0 |
Wait for Post-Tx Timer #2 after transmitting |
PRE_WAIT_POST_TX_TIMER_1 |
25 | UFix1_0 |
Wait for Post-Tx Timer #1 before transmitting |
PRE_WAIT_POST_RX_TIMER_1 |
24 | UFix1_0 |
Wait for Post-Rx Timer #1 before transmitting |
NUM_SLOTS |
23:8 | UFix16_0 |
Number of backoff slots to use if pre-Tx deferral is required |
PKT_BUF |
3:0 | UFix4_0 |
Tx pkt buf index for new Tx |
Register TX_CTRL_B_PARAMS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
REQUIRE_ZERO_NAV |
11 | UFix1_0 |
Skip transmission if NAV is nonzero |
POST_WAIT_POST_TX_TIMER_1 |
10 | UFix1_0 |
Wait for Post-Tx Timer #1 after transmitting |
PRE_WAIT_POST_RX_TIMER_2 |
9 | UFix1_0 |
Wait for Post-Rx Timer #2 before transmitting |
PRE_WAIT_POST_RX_TIMER_1 |
8 | UFix1_0 |
Wait for Post-Rx Timer #1 before transmitting |
PKT_BUF |
3:0 | UFix4_0 |
Tx pkt buf index for new Tx |
Register TX_CTRL_C_PARAMS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
NUM_SLOTS |
27:12 | UFix16_0 |
Number of backoff slots for pre-Tx deferral |
REQ_BACKOFF |
8 | UFix1_0 |
Require a new backoff before transmitting |
PKT_BUF |
3:0 | UFix4_0 |
Tx pkt buf index for new Tx |
Register TX_CTRL_D_PARAMS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
NUM_SLOTS |
27:12 | UFix16_0 |
Number of backoff slots for pre-Tx deferral |
REQ_BACKOFF |
8 | UFix1_0 |
Require a new backoff before transmitting |
PKT_BUF |
3:0 | UFix4_0 |
Tx pkt buf index for new Tx |
Register TX_CTRL_STATUS
¶
Name | Bits | Datatype | Description |
---|---|---|---|
POSTRX_TIMER1_RUNNING |
23 | UFix1_0 |
Post-Rx Timer #1 is running |
POSTRX_TIMER2_RUNNING |
22 | UFix1_0 |
Post-Rx Timer #2 is running |
POSTTX_TIMER1_RUNNING |
21 | UFix1_0 |
Post-Tx Timer #1 is running |
POSTTX_TIMER2_RUNNING |
20 | UFix1_0 |
Post-Tx Timer #2 is running |
TX_D_STATE |
23:21 | UFix3_0 |
Tx controller D current state |
TX_D_DONE |
20 | UFix1_0 |
Tx controller D is done |
TX_D_PENDING |
19 | UFix1_0 |
Tx controller D is running |
TX_C_STATE |
18:16 | UFix3_0 |
Tx controller C current state |
TX_C_DONE |
15 | UFix1_0 |
Tx controller C is done |
TX_C_PENDING |
14 | UFix1_0 |
Tx controller C is running |
TX_B_STATE |
13:11 | UFix3_0 |
Tx controller B current state |
TX_B_RESULT |
10:9 | UFix2_0 |
Tx controller B result code |
TX_B_DONE |
8 | UFix1_0 |
Tx controller B is done |
TX_B_PENDING |
7 | UFix1_0 |
Tx controller B is running |
TX_A_STATE |
6:4 | UFix3_0 |
Tx controller A current state |
TX_A_RESULT |
3:2 | UFix2_0 |
Tx controller A result code |
TX_A_DONE |
1 | UFix1_0 |
Tx controller A is done |
TX_A_PENDING |
0 | UFix1_0 |
Tx controller A is running |
Register TX_PKT_BUF_SEL
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_BUF_ADDR_OFFSET |
23:16 | UFix8_0 |
Defines address of first MAC payload byte in Tx pkt buffers |
Register TX_START
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_CTRL_D_START |
3 | UFix1_0 |
Start Tx controller D |
TX_CTRL_C_START |
2 | UFix1_0 |
Start Tx controller C |
TX_CTRL_B_START |
1 | UFix1_0 |
Start Tx controller B |
TX_CTRL_A_START |
0 | UFix1_0 |
Start Tx controller A |
Register TX_TIMESTAMP_MSB
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_TIMESTAMP_LSB |
31:0 | UFix32_0 |
32 LSB of 64-bit MAC time at last TX_START |
Register TX_TIMESTAMP_MSB
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_TIMESTAMP_MSB |
31:0 | UFix32_0 |
32 MSB of 64-bit MAC time at last TX_START |
Register TX_WVFM_CFG_L
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_WVFM_CFG_LSB |
31:0 | UFix32_0 |
32 LSB of waveform config for next Tx |
Register TX_WVFM_CFG_M
¶
Name | Bits | Datatype | Description |
---|---|---|---|
TX_WVFM_CFG_MSB |
31:0 | UFix32_0 |
32 MSB of waveform config for next Tx |