MAC Core Interface

The MAC IP core must be instantiated in the FPGA design along with other required cores. The MAC core also requires a CPU in the FPGA design for configuration and control from software.

The MAC core port are described below.

Clocks and Resets

The MAC core has a single clock domain that must be synchronous to the IQ sample stream.

Port	Direction	Data Type	Description
clk	Input	UFix1_0	Clock input, must be same clock used for wlan_mac_hw.clk; typically this is connected to a 160MHz clock that is synchronized to the radio reference clock.
wlan_mac_hw_aresetn	Input	UFix1_0	Asynchronous active-low reset for AXI interface logic. This reset does not clear registers in the AXI slave interface. This signal should be connected to the same reset as the AXI infrastructure cores.

AXI Memory Mapped Slave Interface

The MAC IP core implements an AXI4-Lite slave interface with many configuration and status registers. The FPGA design must connect this AXI slave interface to an AXI master, typically an AXI interconnect and CPU. The CPU must configure the MAC IP core at boot by writing the core’s registers.

The MAC core’s AXI interface appears as a bus named wlan_mac_hw_regs_s_axi in the Vivado tools. This bus interface wraps all the inputs/outputs which implement the AXI interface.

AXI Stream Interfaces

The MAC core uses many AXI stream interfaces to interact with external IP cores. Every stream interface uses the core’s single clk - any clock-crossing logic must be implemented externally.

Interface	Direction	Data Width	Description
m_axis_rx_hdr_info	Master	32	Reports MAC Header Rx events to the MAC software, typically via an external stream-to-memory-mapped FIFO.
m_axis_rx_mpdu_bytes	Master	8	MAC payload bytes for received frames/subframes that passed the configured filters, typically routed to an external DMA.
m_axis_rx_mpdu_metadata	Master	32	Information about each packet whose payload is passed to m_axis_rx_mpdu_bytes, typically routed to a stream-to-memory-mapped FIFO for use by the driver.
m_axis_rx_pkt_dma_cmd	Master	72	DMA commands, one issued for each packet whose payload will be output on m_axis_rx_mpdu_bytes.
m_axis_tx_data	Master	8	MAC payload bytes for current waveform, must be routed to the Tx PHY core.
m_axis_tx_wvfm_cfg	Master	64	Waveform parameters to be used by Tx PHY for next transmission, must be routed to Tx PHY core.
m_axis_tx_wvfm_cfg	Master	64	Waveform parameters to be used by Tx PHY for next transmission, must be routed to Tx PHY core.
s_axis_rx_buf_addrs	Slave	32	Physical memory addresses provided by driver, used to construct commands for Rx DMA.
s_axis_rx_data	Slave	8	Raw MAC payload bytes output from Rx PHY core.

BRAM Interfaces

The MAC core connects to external dual-port BRAM blocks to exchange data with the MAC software. The MAC core implements the BRAM master spec and connects to one port of each BRAM. The other port of each BRAM is connected to an external BRAM interface controller which maps the BRAM into the CPU address space.

Port	Direction	Description
bram_tx_*	BRAM Master	Tx packet buffer BRAM interface. The MAC core retrieves packet bytes from the packet buffer configured in a Tx controller. The packet buffer contents are written by an external DMA as directed by the MAC software.
bram_mac_hdr_*	BRAM Master	MAC header buffer BRAM interface. The MAC core writes received MAC headers to BRAM for parsing by the MAC software.

Interrupt Outputs

The MAC core has two interrupt outputs that must be connected to the system’s interrupt controller.

Port	Sensitivity	Description
interrupt_a	LEVEL_HIGH	Software-configured interrupt selects from Tx controller and TBTT events; typically routed to the MAC software interrupt controller.
interrupt_b	LEVEL_HIGH	Software-configured interrupt selects from TBTT events; typically routed to the MAC software and/or driver interrupt controllers.

PHY Core Interfaces

The following ports must be connected to the Tx/Rx PHY cores in the FPGA design.

Port	Direction	Data Type	Description
phy_rx_block_pktdet	Output	UFix1_0	When asserted blocks any new receptions, does not interrupt ongoing reception. Asserted by MAC hardware to ensure a reception is not overwritten before it is processed by software.
phy_cca_ind_busy	Input	UFix1_0	Indicates Rx PHY observes a busy medium, connected to MAC hardware’s CCA logic.
phy_rx_start_ind	Input	UFix1_0	Asserts when Rx PHY has started receiving a new packet
phy_rx_end_ind	Input	UFix1_0	Asserts at MAC’s RX_END event (extension period after last sample on medium)
phy_rx_end_rxerror	Input	UFix2_0	Asserts when an Rx event ends with an error, typically a decoding error in the PHY header
phy_rx_phy_hdr_ind	Input	UFix1_0	Asserts when a PHY header has been decoded and can safely be processed by MAC software
phy_rx_phy_hdr_length	Input	UFix16_0	LENGTH field decoded from PHY header, valid when phy_rx_phy_hdr_ind is asserted
phy_rx_phy_hdr_mcs	Input	UFix7_0	MCS field decoded from PHY header, valid when phy_rx_phy_hdr_ind is asserted
phy_rx_phy_hdr_aggregate	Input	UFix1_0	AGGREGATE field decoded from PHY header, valid when phy_rx_phy_hdr_ind is asserted
phy_rx_phy_hdr_phy_mode	Input	UFix2_0	Waveform type (0=DSSS, 1=NONHT, 2=HTMF) of received packet, valid when phy_rx_phy_hdr_ind is asserted
phy_rx_phy_hdr_unsupported	Input	UFix1_0	Asserts when PHY header indicates packet requires features not supported by PHY, valid when phy_rx_phy_hdr_ind is asserted
phy_rx_gain_index	Input	UFix8_0	Value of rf_gain_index input captured when the Rx PHY begins processing a new waveform, can be used by MAC software to estimate Rx power on platforms where radio provides a real-time gain index
phy_rx_iq_mag_rfab	Input	UFix32_0	IQ magnitude of the RF A (16LSB) and B (16MSB) streams captured when the Rx PHY begins processing a new waveform, can be used by MAC software to improve Rx power estimates
phy_tx_started	Input	UFix1_0	Asserts when the Tx PHY has started a waveform transmission
phy_tx_done	Input	UFix1_0	Asserts when the Tx PHY has finished a waveform transmission

Debug Signals

The Rx PHY connects many internal signals to top-level ports identified by the dbg_ prefix. These ports can be routed to top-level FPGA pins or on-chip ILA cores for easier debugging in hardware. The selection of ports varies with Rx PHY core version.